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1 typical a pplica t ion descrip t ion 20v in , dual 4a or single 8a dc/dc module regulator the lt m ? 4642 is a complete dual 4a or single 8a step-down dc/dc module ? (micromodule) regulator. included in the package are the switching controller, power fets, inductor, and all support components. operating over input voltage ranges of 4.5v to 20v, (2.375v min with external cpwr bias), the LTM4642 supports two outputs with voltage ranges of 0.6v to 5.5v , set by a single external resistor. its high efficiency design delivers 4a continuous current (5a peak) for each output. high switching frequency and a valley current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. the two outputs are interleaved with 180 phase to minimize the ripple noise and reduce the i/o capacitors. the power module is offered in a 9mm 11.25mm 4.92mm bga package. the LTM4642 is rohs compliant with pb-free finish. dual 4a 1v and 1.2v dc/dc module regulator fea t ures a pplica t ions n small form factor dual 4a power supply n wide input voltage range: 4.5v to 20v (2.375v min with cpwr bias) n dual 180 out-of-phase outputs with 4a dc n dual outputs with 0.6v to 5.5v range n output voltage tracking n 1.5% maximum total dc output voltage error n up to 95% maximum efficiency n phase-lockable fixed frequency 600khz to 1.4mhz n constant on-time, valley current mode architecture n selectable burst mode ? operation n output overvoltage and overcurrent protection n 9mm 11.25mm 4.92mm bga package n telecom and networking equipment n servers n fpga power efficiency vs load current at 12v input l , lt, ltc, ltm, linear technology, the linear logo, burst mode, module and ltpowercad are registered trademarks of analog devices, inc. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 8163643. + v in1 v in2 cpwr sgnd pins not used: comp1, comp2, phasemd, clkout, extv cc , sw1, sw2 gnd LTM4642 4.7f 22f 2 47f 470pf v out1 470pf v out2 100f 0.1f v in 4.75v to 20v 2.2 drv cc intv cc run1 133k 10k 90.9k 61.9k 60.4k 4642 ta01a 10k v rng1 run2 pgood1 pgood2 track/ss1 track/ss2 mode/pllin intv cc v out1 v out1 1v at 4a load v out2 v outs1 freq v outs ? v fb2 v fb1 v out2 1.2v at 4a load intv cc + 47f 100f 0.1f load current (a) 0 70 efficiency (%) 75 80 85 1 2 3 4 4642 ta01b 90 0.5 1.5 2.7 3.5 1.2v (650khz) 1v (650khz) LTM4642 4642fb for more information www.linear.com/LTM4642
2 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v i n1 , v i n2 , sw1, sw2, cpwr .................... C 0.3 v to 22v intv cc , drv cc , pgoo d1 ,2, ru n1 ,2, extv cc , v fb1 , v fb2 (note 4) .................... C 0.3 v to intv cc + 0.3v com p1 , com p2 (note 4) .......................... C 0. 3v to 2.7v mode/pllin, freq, phasmd, v rn g1 ......................................... C 0.3 v to intv cc + 0.3v v out1 , v out2 , v out s1 ................................... C 0.3 v to 6v v outs C ....................................................... 0.3 v to 2.75v tk/s s1 , tk/s s2 ............................................. 0. 3v to 5v internal operating temperature range (note 2) .................................................. C 40 c to 125 c maximum reflow body temperature .................... 24 5 c storage temperature range .................. C 55 c to 125 c (note 1) 1 a h g f e d c v out2 gnd sw2 run2 phasmd comp2 clkout run1 sw1 comp1 freq sgnd v outs ? v out1 mode/pllin cpwr pgood2 track/ss2 track/ss1 gnd gnd gnd gnd gnd v in2 v fb2 v fb1 pgood1 drv cc extv cc intv cc v rng1 v in1 b 2 3 4 5 6 7 bga package 56-lead (9mm 11.25mm 4.92mm) v outs1 t jmax = 125c, e ja = 15c/w, e jp = 4c/w e ja derived from 95mm = 76mm pcb with 4 layers weight = 1.2635g symbol parameter conditions min typ max units v in(dc) input dc voltage v in 4.5v, connect cpwr to a bias > 4.5v l 2.375 20 v v out1,2(range) output voltage range v in = 6v to 20v l 0.6 5.5 v v out1,2(dc) output voltage, total variation with line and load c in = 10f =2, c out = 47f ceramic, 100f poscap, r set = 40.2k? v in = 12v, v out = 1.5v, i out = 4a l 1.4775 1.5 1.5225 v input specifications i inrush(vin) input inrush current at start-up i out = 0a, c in = 10f, c out = 47f ceramic and 100f poscap, v out = 1.5v v in = 12v 0.25 a o r d er i n f or m a t ion e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full internal operating temperature range (note 2), otherwise specifications are at t a = 25c, v in = 12v. per typical application in figure 27. specified as each channel. (note 3) part number pad or ball finish part marking* package type msl rating temperature range (see note 2) device finish code LTM4642ey#pbf sac305 (rohs) LTM4642y e1 bga 3 C40c to 125c LTM4642iy#pbf sac305 (rohs) LTM4642y e1 bga 3 C40c to 125c LTM4642iy snpb (63/37) LTM4642y e0 bga 3 C40c to 125c ? consult marketing for parts specified with wider operating temperature ranges. *pad or ball finish code is per ipc/jedec j-std-609. ? terminal finish part marking: www.linear.com/leadfree ? recommended lga and bga pcb assembly and manufacturing procedures: www.linear.com/umodule/pcbassembly ? lga and bga package and tray drawings: www.linear.com/packaging http://www.linear.com/product/LTM4642#orderinfo LTM4642 4642fb for more information www.linear.com/LTM4642
3 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full internal operating temperature range (note 2), otherwise specifications are at t a = 25c, v in = 12v. per typical application in figure 27. specified as each channel. (note 3) symbol parameter conditions min typ max units i cpwr cpwr bias current cpwr = 12v, mode = continuous 20 ma i q(vin) input supply bias current v in = 12v, v out1 = 1.5v, switching continuous v in = 12v, v out2 = 1.5v, switching continuous v in = 20v, v out1 = 1.5v, switching continuous v in = 20v, v out2 = 1.5v, switching continuous shutdown, run = 0, v in = 12v 25 25 22 22 10 ma ma ma ma a i q(vin) input supply bias current v in = 12v, v out = 1.5v, i out = 4a v in = 20v, v out = 1.5v, i out = 4a 0.6 0.356 a a drv cc internal v cc voltage 6v < v in < 20v, no load 5 5.3 5.6 v i drvcc(reg) drv cc load regulation i drvcc = 0 to 100ma C1.5 C3 % extv cc(hys) extv cc switchover hysteresis 200 mv extv cc extv cc switchover voltage extv cc ramping positive 4.4 4.6 4.8 v output specifications i out1,2(dc) output continuous current range v in = 12v, v out = 1.5v (note 5) 0 4 a v out1(line) v out(nom) line regulation accuracy v out = 1.5v, v in from 4.5v to 20v, i out = 0a for each output l 0.1 0.2 % v out2(load) v out2(nom) load regulation accuracy for each output, v out = 1.5v, 0a to 4a (note 5) v in = 12v l 0.3 0.5 % v out1,2(ac) output ripple voltage i out = 0a, c out = 100f x5r ceramic v in = 12v, v out = 1.5v v in = 20v, v out = 1.5v 15 15 mv mv f s output ripple voltage frequency i out = 2a, v in = 12v, v out = 1.5v, freq = 49.9k to ground 800 khz v out(start) turn-on overshoot c out = 100f and 47f x5r ceramic, v out = 1.5v, i out = 0a v in = 12v v in = 20v 10 10 mv mv t start turn-on time c out = 100f x5r and 47f ceramic, v out = 1.5v, i out = 0a resistive load, track/ss = 10nf v in = 12v 6 ms v out(ls) peak deviation for dynamic load load: 0% to 50% to 0% of full load c out = 100f and 47f x5r ceramic, v out = 1.5v, v in = 12v 50 mv t settle settling time for dynamic load step load: 0% to 50% to 0% of full load c out = 100f and 47f x5r ceramic, v out = 1.5v, v in = 12v 15 s i out(pk) output current limit c out = 100f and 47f x5r ceramic, v in = 6v, v out = 1.5v v in = 20v, v out = 1.5v 7 7 a a control section v outs1(reg) regulated differential feedback v outs1 -v outs C sensed at load point with resistive divider l 0.592 0.6 0.608 v i vouts1 v outs1 input bias current (note 4) 5 25 na i vouts C v outs C input bias current (note 4) C25 C50 na i vfb2 v fb2 input bias current (note 4) C5 50 na v fb2 voltage at v fb2 pin i out = 0a, v out = 2.5v l 0.592 0.6 0.608 v LTM4642 4642fb for more information www.linear.com/LTM4642
4 elec t rical charac t eris t ics the l denotes the specifications which apply over the full internal operating temperature range (note 2), otherwise specifications are at t a = 25c, v in = 12v. per typical application in figure 27. specified as each channel. (note 3) symbol parameter conditions min typ max units i track/ss1,2 soft-start charge current 0v < track/ss1,2 < 0.6v 1.0 a df max maximum duty factor in dropout (note 4) 97 % t on(min) minimum on-time (note 4) 30 ns t off(min) minimum off-time (note 4) 90 ns f low low frequency r freq = 61.9k 600 650 700 khz f nom nominal frequency r freq = 49.9k 730 800 850 khz f high highest frequency r freq = 27.5k 1250 1400 1500 khz r mode/pllin mode/pllin input resistance 600 k v pllin(high) mode/pllin clock in high 2 v v pllin(low) mode/pllin clock in low 0.5 v v run1, 2 run pin on/off threshold run rising l 1.1 1.2 1.3 v v run1, 2(hys) run1, 2, threshold hysteresis delta run rising to run falling 200 mv i run1,2 run pin pull-up current when off run1,2 at sgnd 1.2 a i run1,2(hys) run1,2 pull-up hysteresis i run1,2(hyst) = i run1,2(on) C i run1,2(off) (note 4) 5 a run1,2 res run1,2 resistance to ground 100 k uvlo undervoltage lockout intv cc falling (note 4) intv cc rising l l 3.3 3.7 4.2 4.5 v v r fb1 , r fb2 resistor between v out and v fb pins for each channel 60.1 60.4 60.7 k? v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 2 a v pgood pgood range v fb ramping negative v fb ramping positive C5 5 C7.5 7.5 C10 10 % % ch 2 phase channel 2 phase (relative to channel 1) phasmd = sgnd phasmd = floating phasmd = int v cc 180 180 240 deg deg deg clkout phase clkout phase (relative to channel 1) phasmd = sgnd phasmd = floating phasmd = int v cc 60 90 120 deg deg deg note 1 : stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTM4642e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the full C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the LTM4642i is guaranteed to meet specifications over the full internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: the two outputs are tested separately and the same testing condition is applied to each output. note 4: 100% tested at wafer level only. note 5: see output current derating curves for different v in , v out and t a . note 6: consult factory for operation down at 2.375v to 2.5v input. operating frequency nominal will be reduced. LTM4642 4642fb for more information www.linear.com/LTM4642
5 typical p er f or m ance c harac t eris t ics 3.3v in to 1.5v out transient response 5v in to 1.5v out transient response 3.3v in to 1v out transient response efficiency vs load current at 3.3v in , ccm mode, external 5v bias 5v in to 1v out transient response efficiency vs load current at 5v in , ccm mode 12v in to 1v out transient response efficiency vs load current at 12v in , ccm mode efficiency vs load current at 20v in , ccm mode (refer to figures 19 and 20) t a = 25c, unless otherwise noted. load current (a) 0 efficiency (%) 92 96 4 4642 g01 88 84 1 2 3 0.5 1.5 2.5 3.5 100 90 94 86 98 3.3v to 2.5v (600khz) 3.3v to 1.8v (600khz) 3.3v to 1.5v (600khz) 3.3v to 1.2v (600khz) 3.3v to 1v (600khz) load current (a) 0 efficiency (%) 80 90 4 4642 g02 70 1 2 3 0.5 1.5 2.5 3.5 100 75 85 95 5v to 3.3v (800khz) 5v to 2.5v (800khz) 5v to 1.8v (750khz) 5v to 1.5v (650khz) 5v to 1.2v (650khz) 5v to 1v (650khz) load current (a) 0 efficiency (%) 80 90 4 4642 g02 70 1 2 3 0.5 1.5 2.5 3.5 100 75 85 95 12v to 5v (1.2mhz) 12v to 3.3v (1mhz) 12v to 2.5v (1mhz) 12v to 1.8v (800khz) 12v to 1.5v (800khz) 12v to 1.2v (650khz) 12v to 1v (650khz) load current (a) 0 efficiency (%) 80 90 4 4642 g04 70 60 1 2 3 0.5 1.5 2.5 3.5 100 75 85 65 95 20v to 1.8v (800khz) 20v to 1.5v (800khz) 20v to 1.2v (650khz) 20v to 1v (650khz) 20v to 5v (1.2mhz) 20v to 3.3v (1mhz) 20v to 2.5v (1mhz) c out = 100f 15m esr poscap, 47f ceramic c ff = 470pf f sw = 600khz 4642 g05 1v out 20mv/div i step = 2a/s 2a/div 20s/div in out c out = 100f 15m esr poscap, 47f ceramic c ff = 470pf f sw = 650khz 4642 g06 i step = 2a/s 2a/div 1v out 20mv/div 20s/div in out c out = 100f 15m esr poscap, 47f ceramic c ff = 470pf f sw = 650khz 4642 g07 i step = 2a/s 2a/div 1v out 20mv/div 20s/div in out c out = 120f 22m esr oscon svp, 47f ceramic c ff = 470pf f sw = 600khz 4642 g08 i step = 2a/s 2a/div 1.5v out 50mv/div 20s/div in out c out = 120f 22m esr oscon svp, 47f ceramic c ff = 470pf f sw = 650khz 4642 g09 i step = 2a/s 2a/div 1.5v out 50mv/div 20s/div in out LTM4642 4642fb for more information www.linear.com/LTM4642
6 typical p er f or m ance c harac t eris t ics 12v in to 2.5v out transient response 5v in to 3.3v out transient response 12v in to 3.3v out transient response 6v in to 5v out transient response 12v in to 5v out transient response clock synchronization 12v in to 1.5v out transient response 3.3v in to 2.5v out transient response 5v in to 2.5v out transient response c out = 120f 22m esr oscon svp, 47f ceramic c ff = 470pf f sw = 800khz 4642 g10 i step = 2a/s 2a/div 1.5v out 50mv/div 20s/div in out c out = 47f ceramic c ff = 68pf f sw = 600khz 4642 g11 i step = 2a/s 2a/div 2.5v out 100mv/div 20s/div in out c out = 47f ceramic c ff = 68pf f sw = 800khz 4642 g12 i step = 2a/s 2a/div 2.5v out 100mv/div 20s/div in out c out = 47f ceramic c ff = 68pf f sw = 1mhz 4642 g13 i step = 2a/s 2a/div 2.5v out 100mv/div 20s/div in out c out = 47f ceramic c ff = 68pf f sw = 800khz 4642 g14 i step = 2a/s 2a/div 3.3v out 100mv/div 20s/div in out 4642 g15 i step = 2a/s 2a/div c out = 47f ceramic c ff = 68pf f sw = 1mhz 3.3v out 100mv/div 20s/div in out input capacitor 680f 10v, low impedance input can use much less c out = 47f ceramic c ff = 68pf f sw = 600khz 4642 g16 i step = 2a/s 2a/div 5v out 100mv/div 20s/div in out c out = 47f ceramic c ff = 68pf f sw = 1.2mhz 4642 g17 i step = 2a/s 2a/div 5v out 100mv/div 20s/div in out 4642 g18 extclk 5v/div v sw1 10v/div v sw2 10v/div 1s/div (refer to figures 19 and 20) t a = 25c, unless otherwise noted. LTM4642 4642fb for more information www.linear.com/LTM4642
7 typical p er f or m ance c harac t eris t ics load regulation and current limit (no airflow) output ripple, 10mv typical shorted output start-up, 20v to 1.5v at 4a 12v to 1.5v at 4a c out = 100f ceramic, 47f ceramic f sw = 800khz 4642 g19 1.5v out 10mv/div 2s/div v in = 20v v out = 1.5v 4642 g20 pgood 5v/div v sw2 20v/div v out 0.5v/div i short 10a/div 50s/div c out = 100f ceramic, 47f ceramic c ss = 0.1f 4642 g21 run2 5v/div v sw2 20v/div v out2 1v/div drv cc intv cc 5v/div 20ms/div load current (a) 0 v out (v) 0.6 1.2 7 4642 g22 0 2 4 6 1 3 5 1.8 0.3 0.9 1.5 4.5v in 12v in 20v in v out = 1.5v f sw = 1mhz mode = ccm (refer to figures 19 and 20) t a = 25c, unless otherwise noted. LTM4642 4642fb for more information www.linear.com/LTM4642
8 p in func t ions gnd ( a4-a7, c2, d1, d5, e1, e5, e7, f7, h4-h7): power ground pins for both input and output returns. phasmd (b4): phase mode selection pin for program - ming clock out phase. see electrical characteristics and applications information sections. mode/pllin (c3 ): mode selection or external synchroni - zation pin. tying this pin to sgnd enables discontinuous mode. tying this pin to int v cc enables forced continuous operation. a clock on the pin will force the controller into the continuous mode of operation and synchronize the internal oscillator. the suitable synchronizable frequency range is 600khz to 1400khz subject to inductor ripple current limits described in the freq/pllfltr pin section. the external clock input high threshold is 2v, while the input low threshold is 0.5v. cpwr ( c7): this pin is the main input power to the control ic. this pin normally connects to the input source directly. this pin can be biased at a voltage greater than 4.5v to allow the v in1 and v in2 to operate down to 2.375v input for applications that operate at 2.5v or 3.3v input. if the bias is less than or equal to 5.3v, connect drv cc to this pin. sgnd ( d2, e2): signal ground pins. return ground path for all analog and low power circuitry. tie a single connec - tion to pgnd in the application. see the recommended layout section. clkout (d4): clock out for synchronizing other regula - tors to the common clock. used for multiphase applica - tions. see applications information section. ext v cc (d6): external power input to controller. when extv cc is higher than 4.7v, the internal 5.3v regulator is disabled and the external source supplies current to reduce the power dissipation in the module. this will improve the efficiency more at high input voltages. intv cc (d7): this pin powers the internal control circuits. tie this pin to drv cc with a 2.2 resistor. this pin requires a few milliamps. package row and column labeling may vary among module products. review each package layout carefully. comp1, comp2 ( e3, d3): current control threshold and error amplifier compensation point. the module has been internally compensated for all i/o ranges. freq (e4): frequency selection pin. tie a resistor from this pin to sgnd to set the frequency of operation between 600khz to 1.4mhz for the specific output voltages. for 3.3v input applications, 650khz is an optimized frequency. for 5v to 20v input applications, the optimized operating frequency for the output voltage is as follows : 0.8v to 1.2v (650khz), 1.5v to 1.8v ( 800khz), 2.0v to 5v ( 1.2mhz), 5v from 20v input (1.4mhz). the resistor equation: r freq k ( ) = 41550 freq khz ( ) C 2.2 drv cc (e6): this pin is the ldo 5.3v regulator output used to power the internal control circuits and mosfet drivers. this pin needs a 4.7f ceramic decoupling capaci - tor to gnd. for input voltages less than or equal to 5.3v, connect this pin directly to the input voltage. v outs1 (f2): output voltage sense point for channel 1 remote sensing. this pin has a 49.9 resistor connected to v out1 . this pin can be connected at the load point for accurate remote sensing. v outs C ( f3 ): remote ground sense pin. connect at remote ground point. v fb1 , v fb2 ( f4, c4): the negative input of the error amplifier. internally, this pin is connected to v out with a 60.4k precision resistor. different output voltages can be programmed with an additional resistor between v fb and sgnd pins. see the applications information section for details. track/ss1, track/ss2 ( f5, c5 ): output voltage tracking and soft-start pins. internal soft-start currents of 1.0a charge the soft-start capacitors. see the applications information section to use the tracking function. pgood1, pgood2 ( f6, c6): output voltage power good indicator. open-drain logic output that is pulled to ground when the output voltage is not within 7.5% of the regula - tion point. in single output parallel operation when v fb2 is tied to intv cc , the pgood2 pin is not to be used. LTM4642 4642fb for more information www.linear.com/LTM4642
9 p in func t ions run1, run2 ( g3, b3): run control pins. a source can be used to enable the run pins with an external pull-up resistor. forcing either of these pins below 1.2v will shut down the corresponding outputs. an additional 5a pull- up current is added to this pin, once the run pin rises above 1.2v . also, active control or pull-up resistors can be used to enable the run pin. the maximum voltage is 6v on these pins. there are 100k resistors on run1,2 to ground. it is recommended to use an external pull-up resistor to v in to enable the run pin. see the applications information section. v rng1 (g4): used at final test. tie to intv cc in normal operation. this pin can also be used to adjust the current limit of channel 1. an external resistive divider from intv cc can be used to set the voltage on the v rng pin between 0.6v to 1v, resulting in a maximum sense voltage between 30mv and 50mv. for applications that require less than 7a of the default peak current limit, the v rng pin voltage can be scaled down to obtain a desired current limit level. v in1 ( g5, g6, 67), v in2 ( b5, b6, b7): power input pins. apply input voltage between these pins and gnd pins. recommend placing input decoupling capacitance directly between v in pins and gnd pins. v out1 ( f1, g1, g2, h1, h2 ), v out2 ( a1, a2, b1, b2, c1): power output pins. apply output load between these pins and pgnd pins. recommend placing output decoupling capacitance directly between these pins and pgnd pins. sw1, sw2 ( h3, a3): switching test pins. these pins are provided externally to check the operation frequency. LTM4642 4642fb for more information www.linear.com/LTM4642
10 s i m pli f ie d b lock diagra m decoupling r equire m en t s symbol parameter conditions min typ max units c in external input capacitor requirement v in = 4.5v to 20v, v out1 = 1.5v, v out2 = 1.5v i out1 = 4a, i out2 = 4a 22 f c out1 c out2 external output capacitor requirement v in = 4.5v to 20v, v out1 = 1.5v, v out2 = 1.5v i out1 = 4a i out2 = 4a 150 150 f f t a = 25c. use figure 1 configuration. figure?1. simplified LTM4642 block diagram c7 0.1f c7 0.1f ss cap c1 22f 25v input voltage source less than 5.3v but greater than 4.5v, connect drv cc and cpwr to v in . input voltage less than 4.5v but greater than 2.375v, provide an external bias to cpwr 5v or greater c4 22f 25v 2.2f 49.9 60.4k r set1 40.2k c out1 mtop1 cpwr pgood1 track1 run1* clkout run1 = 100k ((min v in /1.3) ? 1) r run1 255k track1 v in1 clkout mode/pllin intv cc phasmd freq phasmd comp1 sgnd comp1 pgood1 1h power control v in1 v in2 v out1 v out1 1.5v/4a v in1 4.5v to 20v v in2 4.5v to 20v v out2 1.2v/4a gnd gnd v outs1 v fb1 v outs ? pgood2 pgood2 v fb1 sw1 r5 2.2 100k r freq 49.9k mbot1 0.1f 1f 60.4k mtop2 1h v out2 gnd gnd v fb2 v fb2 r set2 60.4k 4642 f01 sw2 sw2 mbot2 + c out2 gnd + c3 47f + + ? ss cap track2 intv cc track2 v rng1 extv cc extv cc drv cc intv cc run2 r run2 255k v in2 100k r4 2.2 4.7f c6 1f c2 1f internal comp comp2 sgnd * absolute maximum = 6v sgnd comp2 internal comp LTM4642 4642fb for more information www.linear.com/LTM4642
11 o pera t ion the LTM4642 is a dual independent input 4a nonisolated switching mode dc/dc power supply. it can deliver up to 4a (dc current) for each output with few external input and output capacitors. this module provides precisely regulated output voltages programmable via external resistors from 0.6v to 5.5v over a 4.5v to 20v input voltage range. the typical application schematic is shown in figure 27. the input voltage source can operate down to 2.375v with an external bias applied to the cpwr pin. the external bias needs to be 5v or higher. see the typical applications schematics for examples. the LTM4642 has integrated constant on-time valley cur - rent mode regulators and built-in power mosfet devices with fast switching speed. to reduce switching noise, the two outputs are interleaved with 180 phase internally and can be synchronized externally using the mode/pllin pin. with current mode control and internal feedback loop compensation, the LTM4642 module has sufficient stabil - ity margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. current mode control provides cycle-by-cycle fast current limit and current foldback in a short-circuit condition. in - ternal overvoltage and undervoltage comparators pull the open-drain pgood pins output low if the output feedback voltage exits a 7.5% window around the regulation point. the power good pin is disabled during start-up. pulling the run pins below 1.2v forces the controller into its shutdown state, by turning off both mosfets. the track/ss pins are used for programming the output voltage ramp and voltage tracking during start-up. see the applications information section. the LTM4642 is internally compensated to be stable over all operating conditions. ltpowercad ? is available for transient and stability analysis. the v fb pins are used to program the output voltage with a single external resistor to ground. multiphase operation can be easily employed with clock synchronization. high efficiency at light loads can be accomplished with selectable discontinuous mode using the mode/pllin pin. efficiency graphs are provided for light load operations in the typical performance characteristics section. LTM4642 4642fb for more information www.linear.com/LTM4642
12 the typical LTM4642 application circuit is shown in figure 27. external component selection is primarily deter - mined by the maximum load current and output voltage. output v oltage programming the p wm controller has an internal 0.6v reference voltage. as shown in the block diagram, a 60.4k internal feedback resistor r fb connects v out to the v fb pin. the output volt - age will default to 0.6v with no feedback resistor. adding a resistor r set from the v fb pin to sgnd programs the output voltage: v out = 0.6v ? 60.4k + r set r set or equivalently: r set = 60.4k v out 0.6v C 1 ? ? ? ? ? ? table 1. r set resistor table vs various output voltages v out (v) 0.6 1.0 1.2 1.5 1.8 2.5 3.3 5 r set (k) open 90.9 60.4 40.2 30.1 19.1 13.3 8.25 v out1 supports feedback voltage referred remote sensing, as such the v outs1 pin can be tied to v out1 at the load sense point, and v outs C is tied to ground at the load sense point. v out2 is programmed with a resistor to ground. for a 2- phase single 8a output, the v fb2 pin can be connected to intv cc to disable the channel 2 error amplifier, and inter - nally connect the comp2 pin to comp1 pin. the comp2 pin can be left floating or connected to com p1 externally. the track/ss2 and pgood2 pins are not functional in this mode, thus they can be left floating. see the typical applications at the end of the data sheet. input capacitors the lt m4642 module should be connected to a low ac- impedance dc source. a 47f to 100f surface mount aluminum electrolytic capacitor can be used for more input bulk capacitance. this bulk capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. for a buck converter, the switching duty-cycle can be estimated as: d = v out v in without considering the inductor ripple current, for each output, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) ? d ? (1 ? d) in the above equation, is the estimated efficiency of the power module. the bulk capacitor can be a switcher-rated aluminum electrolytic capacitor or a polymer capacitor. one 22f ceramic input capacitor is typically rated for 2a of rms ripple current, so the rms input current at the worst case for each output at 4a maximum current is about 2a. if a low inductance plane is used to power the device, then two 22f ceramic capacitors are enough for both outputs at 4a load and no external input bulk capacitor is required. output capacitors the LTM4642 is designed for low output voltage ripple noise. the bulk output capacitors defined as c out are chosen with low enough effective series resistance (esr) to meet the output voltage ripple and transient require - ments. c out can be a low esr tantalum capacitor, a low esr polymer capacitor or ceramic capacitor. the typical output capacitance range for each output is from 47f to 220f . additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spikes is required. ltpowercad is available for stability analysis. multiphase operation will reduce effective output ripple as a function of the number of phases. application note 77 discusses this noise re - duction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. ltpowercad calculates the output ripple reduction as the number of implemented phases increased by n times. see table 6 for output capacitor suggestions. a pplica t ions i n f or m a t ion LTM4642 4642fb for more information www.linear.com/LTM4642
13 mode selections and phase-locked loop the LTM4642 can be enabled to operate in discontinuous or forced continuous mode. to select the forced continuous operation, tie the mode/pllin pin to intv cc . to select discontinuous operation, or tie the mode/pllin pin to ground. this will improve the light load efficiency. frequency selection and external clock synchronization an internal oscillator (clock generator) provides phase interleaved internal clock signals for individual channels to lock on to. the switching frequency and phase of each switching channel is independently controlled by adjust - ing the top mosfet turn-on time (on-time) through the one-shot timer . this is achieved by sensing the phase relationship between a top mosfet turn-on signal and its internal reference clock through a phase detector, and the time interval of the one-shot timer is adjusted on a cycle-by-cycle basis, so that the rising edge of the top mosfet turn-on is always trying to synchronize to the internal reference clock signal for the respective channel. the frequency of the internal oscillator can be programmed from 600khz to 1.4mhz by connecting a resistor, r freq , from the freq pin to signal ground (sgnd). the equation: r freq k ( ) = 41550 freq khz ( ) C 2.2 for applications with stringent frequency or interference requirements, an external clock source connected to the mode/pllin pin can be used to synchronize the internal clock signals through a clock phase-locked loop (clock pll). the LTM4642 operates in forced continuous mode of operation when it is synchronized to the external clock. the external clock frequency has to be within 30% of the internal oscillator frequency for successful synchroniza - tion. the clock input levels should be no less than 2v for high and no greater than 0.5v for low. the mode/ pllin pin has an internal 600k pull-down resistor. phasmd pin programming the phasmd pin determines the relative phases between the internal reference clock signals for the two channels applica t ions in f or m a t ion as well as the clkout signal, as shown in table 2. the phases tabulated are relative to zero degree (0) being defined as the rising edge of the internal reference clock signal of channel 1. the clkout signal can be used to synchronize additional power regulator modules. the system can be configured for up to 12-phase operation with a multichannel solution. typical configurations are shown in table 3 to interleave the phases of the channels. the applications will validate a 6 phase multiple regulator solution with multiple outputs. each of the LTM4642 channels can be paralleled up to 8a of output, but cannot be paralleled from one module to the other modules. twelve phases can be paralleled with no more than two phases per module. table 2 phasmd sgnd float intvcc channel 1 0 0 0 channel 2 180 180 240 clkout 60 90 120 table 3 number of phases number of LTM4642* pin connections [pin name (chip number)] 2 1 phasmd(1) = floa t or sgnd 3 2 or 1 + ?(LTM4642) phasmd(1) = int v cc mode/pllin(2) = clkout(1) 4 2 phasmd(1) = floa t phasemd(2) = float or sgnd mode/pllin(2) = clkout(1) 6 3 phasmd(1) = sgnd phasmd(2) = sgnd mode/pllin(2) = clkout(1) phasmd(3) = floa t or sgnd mode/pllin(3) = clkout(2) *no more than two channels of any one module may be paralleled. soft-start and tracking the LTM4642 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. when one particular channel is configured to soft-start by itself, a capacitor should be connected to its track/ss pin. this channel is in the shutdown state if its run pin voltage is below 1.2v. its track/ss pin is actively pulled to ground in this shutdown state. LTM4642 4642fb for more information www.linear.com/LTM4642
14 a pplica t ions i n f or m a t ion figure?2. example of coincident tracking v track is the track ramp applied to the slaves track/ss2 pin. v track has a control range of 0v to 0.6v. when the master s output is divided down with the same resistor values used to set the slaves output, then the slave will coincident track with the master until it reaches its final value. the master will continue to its final value from the slaves regulation point. ratiometric modes of tracking can be achieved by select - ing different divider resistors values to change the output tracking ratio. the master output must be greater than the once the run pin voltage is above 1.2v , the channel pow - ers up. a soft-start current of 1a then starts to charge its soft-start capacitor . note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the track/ss pin. current foldback is disabled during this phase to ensure smooth soft-start or tracking. the soft-start or tracking range is defined to be the voltage range from 0v to 0.6v on the track/ss pin. the total soft-start time can be calculated as : t soft-start = 0.6v ? c ss f ( ) 1a output voltage tracking can be programmed externally using the track/ss pin. the master channel is divided down with an external resistor divider that is the same as the slave channels feedback divider to implement co - incident tracking. the LTM4642 uses an accurate 60.4k resistor internally for the top feedback resistor . figure? 2 shows an example of coincident tracking. figure?3 shows the output voltages with coincident tracking. v slave = 1 + r1 r2 ? ? ? ? ? ? ? v track figure?3. coincident tracking + v in1 v in2 cpwr sgnd gnd LTM4642 4.7f c out1 47f 470pf 470pf v out1 v out2 c out2 100f c in1 22f c in2 22f 0.1f v in 4.75v to 20v 2.2 drv cc intv cc run1 131k r2 90.9k r1 60.4k 10k r fb1 40.2k r fb2 90.9k r freq 61.9k 4642 f02 10k v rng1 run2 pgood1 pgood2 track/ss1 track/ss2 v out1 mode/pllin intv cc v out1 v out1 1.5v at 4a load v out2 v outs1 freq v outs ? v fb2 v fb1 v out2 1.0v at 4a load pgood1 pgood2 intv cc + c out4 100f c out3 47f pins not used: comp1, comp2, phasemd, clkout, extv cc , sw1, sw2 time output voltage 4642 f03 master output slave output LTM4642 4642fb for more information www.linear.com/LTM4642
15 slave output for the tracking to work. master and slave data inputs can be used to implement the correct resistors values for coincident or ratiometric tracking. multiphase operation multiphase operation with the LTM4642 two regulator channels in parallel will lower the effective input rms ripple current as well as the output ripple current due to the interleaving operation of the regulators. figure?4 provides a ratio of input rms ripple current to dc load current as a function of duty cycle and the number of paralleled phases. choose the corresponding duty cycle and the number of phases to get the correct ripple current value. for example, the 2-phase parallel for one LTM4642 design provides 8a at 2.5v output from a 12v input. the duty cycle is dc = 2.5v/12v = 0.21. the 2- phase curve has a ratio of ~0.25 for a duty cycle of 0.21. this 0.25 ratio of rms ripple current to a dc load current of 8a equals ~2a of input rms ripple current for the external input capacitors. no more than two phases of a module may be paralleled. the effective output ripple current is lowered with multiphase operations as well. figure?5 provides a ratio of peak-to-peak output ripple current to the normalized output ripple current as a function of duty cycle and the number of paralleled phases. choose the corresponding duty cycle and the number of phases to get the correct output ripple current ratio value. if a 2-phase operation is chosen at 12v in to 2.5v out with a duty cycle of 21%, then 0.6 is the ratio of the normalized output ripple current to inductor ripple dir at the corresponding duty cycle. this leads to ~1.3a of the effective output ripple current i l if the dir is at 2.2a. refer to application note 77 for a detailed explanation of the output ripple current reduction as a function of paralleled phases. the output ripple voltage has two components that are related to the amount of bulk capacitance and effective series resistance (esr) of the output bulk capacitance. therefore, the output ripple voltage can be calculated with the known effective output ripple current. the equation: v out(p-p) i l /(8 ? f ? n ? c out ) + esr ? i l where f is frequency and n is the number of parallel phases. a pplica t ions i n f or m a t ion run pin the run pins can be used to enable or sequence the particular regulator channel. the run pins have their own internal 1.2a current source to pull up the run pins to 1.2v, and the current will increase to 5a above 1.2v . board contamination or residue can load down these small pull-up currents, so a 100k resistor is placed from the run pins to ground. this 100k resistor can be used with a resistor to v in to set the turn-on threshold for the run pins the resistor divider needs to be low enough resistance to swamp out the pull-up current sources to prevent unintended activation of the device. the run pin has a maximum rated voltage of 6v . see figure?1 block diagram for set turn on equation. power good the pgood pin is connected to the open drain of an internal n-channel mosfet. the mosfet turns on and pulls the pgood pin low when either v fb pin voltage is not within 7.5% of the 0.6v reference voltage. the pgood pin is also pulled low when either run pin is below 1.2v or when the LTM4642 is in the soft-start or tracking phase. when the v fb pin voltage is within the 7.5% requirement, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6v. the pgood pin will flag power good immediately when both v fb pins are within the 7.5% window. however, there is an internal 17s power bad mask when either v fb goes out of the 7.5% window. in parallel single output operation, only use pgood1. cpwr, drv cc , intv cc and extv cc the cpwr is the main power input to the internal control ic. this pin is normally connected to the input voltage source. this pin can be biased with a 5v supply when operating at input voltages below 4.5v. when 4.5v < v in < 5.3v, then tie cpwr to drv cc . see the typical applications. the drv cc is the internal 5.3v regulator that powers the LTM4642 internal mosfet drivers for the internal power mosfets. the drv cc requires a 4.7f ceramic capacitor to ground. intv cc powers the internal controller circuits and is connected to drv cc through a 2.2 resistor. this intv cc bias is 20ma. LTM4642 4642fb for more information www.linear.com/LTM4642
16 applica t ions in f or m a t ion duty cycle (v out /v in ) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4642 f04 rms input ripple current dc load current 6-phase 4-phase 3-phase 2-phase 1-phase duty cycle (v out /v in ) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4642 f05 peak-to-peak output ripple current dir ratio = 6-phase 4-phase 3-phase 2-phase 1-phase figure?4. normalized input rms ripple current vs duty cycle for one to six phases* *t he LTM4642 can only have the two channels per module p aralleled figure?5. normalized output ripple current vs duty cycle, dlr = v out t/l LTM4642 4642fb for more information www.linear.com/LTM4642
17 applica t ions in f or m a t ion a 5v output on channel 1 or 2 can be used to power the extv cc pin when the input voltage is at the high end of the supply range to reduce power dissipation in the module. for example, the dropout voltage for 20v input would be 20v C 5v = 15v . this 15v headroom then multiplied by the power mosfet drive current of ~30ma would equal ~0.45w additional power dissipation. so utilizing a 5v output on the extv cc would improve design efficiency and reduce device temperature rise. otherwise try to operate cwpr off of a 5v bias when operating at higher supply voltages. see the typical applications section. fault conditions: current limit and overcurrent foldback the LTM4642 has a current mode controller, which inher - ently limits the cycle-by-cycle inductor current not only in steady-state operation, but also in transient. t o further limit current in the event of an overload condi - tion, the LTM4642 provides foldback current limiting. if the output voltage falls by more than 50%, then the maximum output current is progressively lowered to one-fourth of its full current limit value. foldback current limiting is disabled during soft-start and tracking up. sw pins the sw pins are generally for testing purposes by moni - toring these pins. these pins can also be used to dampen out switch node ringing caused by lc parasitic in the switched current paths. usually a series r-c combina - tion is used called a snubber circuit. the resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor . if the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. the inductance is usually easier to predict. it combines the power path board inductance in combination with the mosfet interconnect bond wire inductance. first the sw pin can be monitored with a wide bandwidth scope with a high frequency scope probe. the ring fre - quency can be measured for its value. the impedance z can be calculated : z (l) = 2fl, where f is the resonant frequency of the ring, and l is the total parasitic inductance in the switch path. if a resistor is selected that is equal to z, then the ringing should be dampened. the snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. calculated by: z ( c ) = 1/(2fc). these values are a good place to start with. modification to these components should be made to attenuate the ringing with the least amount of power loss. thermal considerations and output current derating in different applications, the LTM4642 operates in a variety of thermal environments. the maximum output current is limited by the environmental thermal condition. sufficient cooling should be provided to ensure reliable operation. when the cooling is limited, proper output current derat - ing is necessary, considering the ambient temperature, a i rflow, input/output conditions, and the need for increased reliability. the two outputs of the LTM4642 are paralleled to charac - terize the output current derating curves. the power loss cur ves in figure? 8 to figure?10 can be used in coordination with load current derating curves in figure?11 to figure?24 for calculating an approximate ja for the module with various cooling methods. application note 103 provides detailed explanation of the analysis for the thermal models and the derating curves. tables 4 and 5 provide a sum - mary of the equivalent ja parameters are correlated to the measured values, and are improved with airflow. the power loss curves are taken at room temperature, and are increased with multiplicative factors according to the ambient temperature. the approximate factors are: 1.35 for 115c and 1.4 for 120c . the derating curves are plotted with ch1 and ch2 paralleled output current starting at 8a and the ambient temperature starting at 50c. the derated output voltages are 1.0v, 2.5v, 3.3v and 5.0v . tables 4 and 5 specify the approximate ja with airflow conditions for 1v and 5v outputs. these two conditions are chosen to include the lower and higher output voltage ranges for cor - relating the thermal resistance, but any derating curve point along with power loss curve can be used to calculate the ja . thermal models are derived from several temperature measurements in a controlled temperature chamber along LTM4642 4642fb for more information www.linear.com/LTM4642
18 applica t ions in f or m a t ion table 4. 1v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 11, 13 5, 12 figures 8, 9 0 none 13 figures 11, 13 5, 12 figures 8, 9 200 none 10 figures 11, 13 5, 12 figures 8, 9 400 none 9 figures 12, 14 5, 12 figures 8, 9 0 bga heat sink 13 figures 12, 14 5, 12 figures 8, 9 200 bga heat sink 8 figures 12, 14 5, 12 figures 8, 9 400 bga heat sink 7.5 table 5. 5v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 21, 23 12, 20 figures 9, 10 0 none 15 figures 21, 23 12, 20 figures 9, 10 200 none 13 figures 21, 23 12, 20 figures 9, 10 400 none 12 figures 22, 24 12, 20 figures 9, 10 0 bga heat sink 14 figures 22, 24 12, 20 figures 9, 10 200 bga heat sink 10 figures 22, 24 12, 20 figures 9, 10 400 bga heat sink 10 heat sink manufacturer part number website cool innovations 3-05040 www.coolinnovations.com chomerics t411 interface www.chomerics.com table 6. output voltage response vs component matrix (refer to figure 27) 0a to 2a load step typical measured values ceramic capacitor vendors value part number bulk vendors value part number esr murata c out : 47f 6.3v, x5r grm21br60j476me15 sanyo oscon svpc c out : 120f 10v 10svpc120mv 22m? murata c out : 47f 10v, x5r grm31cr61a476ke15 panasonic sp c out : 100f 6.3v eefctoj101r 15m? murata c in : 22f, x7r, 16v grm32er71c226kea8 v out (v) c in (ceramic) c in (bulk)** c out1 (ceramic) c out2 (cer and bulk) c ff (pf) v in (v) droop (mv) peak to peak recovery time (s) load step (a/s) r fb (k?) freq (khz) 1 22f 2 56f 47f 100f or 120f 470 3.3, 5, 12 31 62 20 2 90.9 650 1.2 22f 2 56f 47f 100f or 120f 470 3.3, 5, 12 30 63 20 2 60.4 650 1.5 22f 2 56f 47f 100f or 120f 470 3.3, 5, 12 35 70 20 2 40.2 700 1.8 22f 2 56f 47f 100f or 120f 470 3.3, 5, 12 38 80 25 2 30.1 750 2.5 22f 2 56f 47f 68 3.3, 5, 12 100 200 20 2 19.1 1000 3.3 22f 2 56f 47f 68 5, 12 120 240 20 2 13.3 1000 5 22f 2 56f 47f 68 185 390 20 2 8.25 1200 ** bulk capacitance is optional if v in has very low input impedance. LTM4642 4642fb for more information www.linear.com/LTM4642
19 applica t ions in f or m a t ion with thermal modeling analysis. the junction temperatures are monitored while ambient temperature is increased with and without air?ow. the power loss increase with ambient temperature change is factored into the derating curves. the junctions are maintained at 120c maximum while lowering output current or power with increasing ambient temperature. the decreased output current will decrease the internal module loss as ambient temperature is increased. the monitored junction temperature of 120c minus the ambient operating temperature speci?es how much module temperature rise can be allowed. as an example in figure?14 the load current is derated to ~7a at ~100c with no air or heat sink and the power loss for the 12v to 1.0v at 7a output is about 1.2w (power loss at 3.5a load multiplied by 2). the 1.2w loss is multiplied by the 1.4 multiplying factor at 120c junction to get 1.68w. if the 100c ambient temperature is subtracted from the 120c junction temperature, then the difference of 20c divided by 1.68w equals a 12c /w thermal resistance. table 4 speci?es a 13c /w value which is very close. table 4 and table 5 provide equivalent thermal resistances for 1.0v and 5v outputs with and without air?ow and heat sinking. the derived thermal resistances in tables 4 and 5 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. the printed circuit board is a 1.6mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. the pcb dimensions are 95mm 76mm. the bga heat sinks are listed below table 5. the thermal resistances reported in the pin configura - tion section of the data sheet are consistent with those parameters defined by je sd51 -12 and are intended for use with finite element analysis (fea) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation per - formed on a module package mounted to a hardware test board defined by je sd51 -9 ( test boards for area array surface mount package thermal measurements ). the motivation for providing these thermal coefficients is found in jesd51-12 (guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the module regulator s thermal performance in their ap - plication at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin con - figuration section are in-and-of themselves not relevant to providing guidance of thermal per formance ; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to ones application-usage, and can be adapted to correlate thermal performance to ones own application. the pin configuration section gives four thermal coeffi - cients explicitly defined in jesd51-12; these coefficients are quoted or paraphrased below : 1. ja , the thermal resistance from junction to ambi - ent, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd51-9 defined test board, which does not reflect an actual application or viable operating condition. 2. jcbottom , the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. in the typical module, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environ - ment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions dont generally match the users application. 3. jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. LTM4642 4642fb for more information www.linear.com/LTM4642
20 applica t ions in f or m a t ion 4. jb , the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module and into the board, and is really the sum of the jcbottom and the thermal re - sistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package, using a two sided, two layer board. this board is described in jesd51-9. a graphical representation of the aforementioned ther - mal resistances is given in figure?6 ; blue resistances are contained within the module regulator , whereas green resistances are external to the module package. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by je sd51 -12 or provided in the pin configuration section replicates or conveys normal operating conditions of a module regulator. for example, in normal board-mounted applications, never does 100% of the devices total power loss (heat) thermally conduct exclusively through the top or exclusively through bot - tom of the module packageas the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the package granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. within the LTM4642, be aware there are multiple power devices and components dissipating power, with a con - sequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. t o reconcile this complication without sacrificing modeling simplicity but also, not ignoring practical realitiesan approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) initially, fea software is used to accurately build the mechanical geometry of the LTM4642 and the specified pcb with all of the cor - rect material coefficients along with accurate power loss sour ce definitions ; (2) this model simulates a software- defined jedec environment consistent with jesd51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec-defined thermal resistance values; (3) the model and fea software is used to evaluate the LTM4642 with heat sink and airflow ; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. an outcome of this 4642 f06 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient resistance (jesd 51-9 defined board) case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance figure?6. graphical representation of jesd51-12 thermal coefficients LTM4642 4642fb for more information www.linear.com/LTM4642
21 applica t ions in f or m a t ion process and due diligence yields a set of derating curves provided in other sections of this data sheet. after these laboratory tests have been performed, then the jb and ba are summed together to correlate quite well with the LTM4642 model with no airflow or heat sinking in a properly define chamber. this jb + ba value is shown in the pin configuration section and should accurately equal the ja value because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink. each system has its own thermal characteristics, therefore thermal analysis must be performed by the user in a particular system. the LTM4642 has been designed to effectively remove heat from both the top and bottom of the package. the bottom substrate material has very low thermal resistance to the printed circuit board and the exposed top metal is thermally connected to the power devices and the power inductors. an external heat sink can be applied to the top of the device for excellent heat sinking with airflow. basically all power dissipating devices are mounted directly to the substrate and the top exposed metal. this provides two low thermal resistance paths to remove heat. safety considerations the LTM4642 modules do not provide galvanic isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. v in (v) v out1 (v) v out2 (v) i load per phase (a) f sw (khz) hot temp peak temp (c) 12 2.5 1.5 4 1000 56.6 figure?7. thermal plot for the specified operation. the temperature rise about 25c ambient is about 30c rise LTM4642 4642fb for more information www.linear.com/LTM4642
22 figure?8. 5v input power loss figure?9. 12v input power loss applica t ions in f or m a t ion figure?10. 20v input power loss current load (a) 0 power loss (w) 0.4 0.8 4 4642 f08 0 1 2 3 3.5 0.5 1.5 2.5 1.0 0.2 0.6 5v to 3.3v 5v to 2.5v 5v to 1.8v 5v to 1.5v 5v to 1.2v 5v to 1v current load (a) 0 power loss (w) 0.4 0.8 4 4642 f09 0 1 2 3 3.5 0.5 1.5 2.5 1.4 1.2 1.0 0.2 0.6 12v to 5v 12v to 3.3v 12v to 2.5v 12v to 1.8v 12v to 1.5v 12v to 1.2v 12v to 1v current load (a) 0 power loss (w) 0.4 0.8 4 4642 f10 0 1 2 3 3.5 0.5 1.5 2.5 2.2 1.4 1.2 1.0 2.0 1.8 1.6 0.2 0.6 20v to 5v 20v to 3.3v 20v to 2.5v 20v to 1.8v 20v to 1.5v 20v to 1.2v 20v to 1v figure?11. 5v in , 1v out 650khz, no heat sink figure?12. 5v in , 1v out 650khz, with heat sink figure?13. 12v in , 1v out 650khz, no heat sink t amb (c) 50 i out(max) (a) 2 120 4642 f11 0 70 90 110 60 80 100 9 5 4 3 8 7 6 1 0 lfm 200 lfm 400 lfm t amb (c) 50 i out(max) (a) 2 120 4642 f12 0 70 90 110 60 80 100 9 5 4 3 8 7 6 1 0 lfm 200 lfm 400 lfm t amb (c) 50 i out(max) (a) 2 120 4642 f13 0 70 90 110 60 80 100 9 5 4 3 8 7 6 1 0 lfm 200 lfm 400 lfm figure?14. 12v in , 1v out 650khz, with heat sink figure?15. 5v in , 3.3v out 650khz, no heat sink figure?16. 5v in , 3.3v out 650khz, with heat sink t amb (c) 50 i out(max) (a) 2 120 4642 f14 0 70 90 110 60 80 100 10 9 5 4 3 8 7 6 1 0 lfm 200 lfm 400 lfm t amb (c) 50 i out(max) (a) 2 120 4642 f15 0 70 90 110 60 80 100 9 5 4 3 8 7 6 1 0 lfm 200 lfm 400 lfm t amb (c) 50 i out(max) (a) 2 120 4642 f16 0 70 90 110 60 80 100 9 5 4 3 8 7 6 1 0 lfm 200 lfm 400 lfm LTM4642 4642fb for more information www.linear.com/LTM4642
23 applica t ions in f or m a t ion figure?17. 12v in , 2.5v out 1mhz, no heat sink figure?18. 12v in , 2.5v out 1mhz, with heat sink figure?19. 20v in , 2.5v out 1mhz, no heat sink figure?20. 20v in , 2.5v out 1mhz, with heat sink figure?21. 12v in , 5v out 1.2mhz, no heat sink figure?22. 12v in , 5v out 1.2mhz, with heat sink figure?23. 20v in , 5v out 1.2mhz, no heat sink figure?24. 20v in , 5v out 1.2mhz, with heat sink t amb (c) 50 i out(max) (a) 2 120 4642 f17 0 70 90 110 60 80 100 9 5 4 3 8 7 6 1 0 lfm 200 lfm 400 lfm t amb (c) 50 i out(max) (a) 2 120 4642 f18 0 70 90 110 60 80 100 9 5 4 3 8 7 6 1 0 lfm 200 lfm 400 lfm t amb (c) 50 i out(max) (a) 2 120 4642 f19 0 70 90 110 60 80 100 9 5 4 3 8 7 6 1 0 lfm 200 lfm 400 lfm t amb (c) 50 i out(max) (a) 2 120 4642 f20 0 70 90 110 60 80 100 9 5 4 3 8 7 6 1 0 lfm 200 lfm 400 lfm t amb (c) 50 i out(max) (a) 2 120 4642 f21 0 70 90 110 60 80 100 9 5 4 3 8 7 6 1 0 lfm 200 lfm 400 lfm t amb (c) 50 i out(max) (a) 2 120 4642 f22 0 70 90 110 60 80 100 9 5 4 3 8 7 6 1 0 lfm 200 lfm 400 lfm t amb (c) 50 i out(max) (a) 2 120 4642 f23 0 70 90 110 60 80 100 9 5 4 3 8 7 6 1 0 lfm 200 lfm 400 lfm t amb (c) 50 i out(max) (a) 2 120 4642 f24 0 70 90 110 60 80 100 9 5 4 3 8 7 6 1 0 lfm 200 lfm 400 lfm LTM4642 4642fb for more information www.linear.com/LTM4642
24 a pplica t ions in f or m a t ion figure?25. recommended pcb layout layout checklist/example the high integration of LTM4642 makes the pcb board layout very simple and easy. however, to optimize its electri - cal and thermal performance, some layout considerations are still necessary . ? use large pcb copper areas for high current path, in - cluding v in1 , v in2 , pgnd, v out1 and v out2 . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci - tors next to the v in , pgnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnections between top layer and other power layers. ? do not put vias directly on the pads. ? use a separated sgnd ground copper area for com - ponents connected to signal pins. connect the sgnd to pgnd underneath the unit. ? decouple the input and output grounds to lower the output ripple noise. figure?25 gives a good example of the recommended layout. c in3 c in4 c in1 v in1 v in2 r fb2 r freq r fb1 ctk/ss1 ctk/ss2 gnd gnd 4642 f25 gnd gnd v out2 v out2 v out1 v out1 gnd gnd c out2 c intvcc c in2 c out2 a 1 2 3 4 5 6 7 b c d e f g h LTM4642 4642fb for more information www.linear.com/LTM4642
25 typical a pplica t ions figure?26. 4.5v to 20v input, 650khz, 0.9v and 1.2v outputs at 4a each figure?27. 5v input, 800khz, 2.5v and 1.8v outputs at 4a each + v in1 v in2 cpwr sgnd gnd LTM4642 4.7f c out1 47f c ff 470pf c ff 470pf v out1 v out2 c out2 100f c in1 22f c in2 22f 0.1f 0.1f v in 4.5v to 20v 2.2 drv cc intv cc run1 131k 10k r fb1 121k r fb2 90.9k r freq 61.9k 4642 f26 10k v rng1 run2 pgood1 pgood2 track/ss1 track/ss2 mode/pllin intv cc pins not used: comp1, comp2, phasemd, clkout, extv cc , sw1, sw2 v out1 v out1 0.9v at 4a load v out2 v outs1 freq v outs ? v fb2 v fb1 v out2 1v at 4a load pgood1 pgood2 intv cc + c out4 100f c out3 47f v in1 v in2 cpwr sgnd gnd LTM4642 4.7f c out1 47f 470pf 470pf v out1 v out2 c in1 22f c in2 22f 0.1f 0.1f v in 5v 2.2 drv cc intv cc run1 131k 10k r fb1 30.2k r fb2 19.1k r freq 49.9k 4642 f27 10k v rng1 run2 pgood1 pgood2 track/ss1 track/ss2 mode/pllin intv cc v out1 v out1 1.8v at 4a load v out2 v outs1 freq v outs ? v fb2 v fb1 v out2 2.5v at 4a load pgood1 pgood2 intv cc c out3 120f oscon svp c out2 47f + pins not used: comp1, comp2, phasemd, clkout, extv cc , sw1, sw2 LTM4642 4642fb for more information www.linear.com/LTM4642
26 figure?28. 1mhz 4-phase, four outputs (3.3v, 2.5v, 1.2v, 0.9v) with tracking to the 3.3v output v in1 v in2 cpwr sgnd gnd LTM4642 4.7f c out3 47f 470pf 68pf v out1 v out2 c in1 22f c in2 22f v in 4.75v to 20v 2.2 drv cc intv cc run1 131k 60.4k 60.4k 19.1k 60.4k 10k r fb1 60.4k r fb2 19.1k r freq 39.2k 10k v rng1 run2 pgood1 pgood2 track/ss1 track/ss2 mode/pllin intv cc1 v out1 1.2v at 4a load v out2 v outs1 freq v outs ? v fb2 v fb1 2.5v at 4a load intv cc1 c out2 100f c out1 47f + v in1 v in2 cpwr sgnd gnd LTM4642 4.7f c out6 47f 470pf 68pf v out1 v out2 4642 f28 c in3 22f c in4 22f 0.1f v in 4.75v to 20v 3.3v 2.2 drv cc intv cc run1 131k 121k 60.4k 10k r fb3 121k r fb2 13.3k r freq1 39.2k 10k v rng1 run2 pgood1 pgood2 track/ss1 track/ss2 mode/pllin intv cc2 v out1 0.9v at 4a load v out2 v outs1 freq v outs ? v fb2 v fb1 3.3v at 4a load intv cc2 c out6 100f c out4 47f + pins not used: comp1, comp2, phasemd, clkout, extv cc , sw1, sw2 t ypical applica t ions LTM4642 4642fb for more information www.linear.com/LTM4642
27 figure?29. output paralleled LTM4642 module for 3.3v at 8a each v in1 v in2 cpwr sgnd gnd LTM4642 4.7f 68pf c in1 22f c in2 22f 0.1f v in 4.75v to 20v 2.2 drv cc intv cc run1 131k r fb1 13.3k r freq 39.2k 1mhz 4642 f29 10k v rng1 run2 pgood1 pgood2 track/ss1 track/ss2 comp1 comp2 mode/pllin intv cc pins not used: phasemd, clkout, extv cc , sw1, sw2 v out1 v out2 v outs1 freq v outs ? v fb2 v fb1 pgood1 3.3v at 8a intv cc intv cc c out1 47f c out2 47f t ypical applica t ions LTM4642 4642fb for more information www.linear.com/LTM4642
28 figure?30. 3.3v input to 1v and 1.8v at 4a each, 1v sequencing 1.8v using pgood1 to enable run2 + v in1 v in2 cpwr sgnd gnd LTM4642 4.7f c out3 47f 470pf 470pf v out1 v out2 c out4 100f c in1 22f c in2 22f 0.1f 0.1f v in 3.3v 2.2 drv cc intv cc run1 100k 10k 3.3v r fb1 90.9k r fb2 30.2k r freq 66.5k 600khz 4642 f30 10k v rng1 run2 pgood1 pgood1 pgood2 track/ss1 track/ss2 mode/pllin intv cc pins used: comp1, comp2, phasemd, clkout, extv cc , sw1, sw2 v out1 v out1 1v at 4a load v out2 v outs1 freq v outs ? v fb2 v fb1 v out2 1.8v at 4a load pgood1 pgood2 intv cc 5v bias (~30ma) + c out2 150f 15m sanyo poscap c out1 47f t ypical applica t ions LTM4642 4642fb for more information www.linear.com/LTM4642
29 table 5. pin assignment p ackage descrip t ion package row and column labeling may vary among module products. review each package layout carefully. pin id function pin id function pin id function pin id function pin id function pin id function a1 v out2 b1 v out2 c1 v out2 d1 gnd e1 gnd f1 v out1 a2 v out2 b2 v out2 c2 gnd d2 sgnd e2 sgnd f2 v outs1 a3 sw2 b3 run2 c3 mode/pllin d3 comp2 e3 comp1 f3 v outs C a4 gnd b4 phasmd c4 v fb2 d4 clkout e4 freq f4 v fb1 a5 gnd b5 v in2 c5 track/ss2 d5 gnd e5 gnd f5 track/ss1 a6 gnd b6 v in2 c6 pgood2 d6 extv cc e6 dvr cc f6 pgood1 a7 gnd b7 v in2 c7 cpwr d7 intv cc e7 gnd f7 gnd pin id function pin id function g1 v out1 h1 v out1 g2 v out1 h2 v out1 g3 run1 h3 sw1 g4 v rng1 h4 gnd g5 v in1 h5 gnd g6 v in1 h6 gnd g7 v in1 h7 gnd LTM4642 4642fb for more information www.linear.com/LTM4642
30 p ackage descrip t ion package top view 4 pin ?a1? corner y x aaa z aaa z detail a package bottom view 3 see notes h g f e d c b a 1234567 pin 1 bga 56 1113 rev ? tray pin 1 bevel package in tray loading orientation component pin ?a1? notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 6. solder ball composition is 96.5% sn/3.0% ag/0.5% cu 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature detail a ?b (56 places) detail b substrate 0.27 ? 0.37 3.95 ? 4.05 // bbb z a a1 b1 ccc z detail b package side view mold cap z m x yzddd m zeee symbol a a1 a2 b b1 d e e f g aaa bbb ccc ddd eee min 4.72 0.50 4.22 0.60 0.60 nom 4.92 0.60 4.32 0.75 0.63 11.25 9.0 1.27 8.89 7.62 max 5.12 0.70 4.42 0.90 0.66 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 56 a2 d e e b f g suggested pcb layout top view 0.000 0.635 1.905 0.635 3.175 1.905 4.445 3.175 4.445 3.810 2.540 1.270 3.810 2.540 1.270 0.3175 0.3175 0.000 4.1275 4.7625 ltmxxxxxx module bga package 56-lead (11.25mm 9.00mm 4.92mm) (reference ltc dwg# 05-08-1961 rev ?) 7 package row and column labeling may vary among module products. review each package layout carefully ! 7 see notes please refer to http://www.linear.com/product/LTM4642#packaging for the most recent package drawings. LTM4642 4642fb for more information www.linear.com/LTM4642
31 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 12/16 absolute maximum rating vfb1, v fb2 changed to intv cc to 0.3v 2 b 6/17 twelve phases can be paralleled with no more than two phases per regulator output 13 LTM4642 4642fb for more information www.linear.com/LTM4642
32 ? linear technology corporation 2016 lt 0617 rev b ? printed in usa www.linear.com/LTM4642 p ackage p ho t ograph r ela t e d p ar t s part number description comments ltm4614 dual, 4a, low v in , dc/dc module regulator 2.375v v in 5.5v, 0.8v v out 5v, 15mm 15mm 2.82mm lga ltm4615 triple, low v in , dc/dc module regulator two 4a outputs and one 1.5a, 15mm 15mm 2.82mm lga, 2.375v v in 5.5v ltm4616 dual, 8a, low v in , dc/dc module regulator 2.7v v in 5.5v, 0.6v v out 5v, 15mm 15mm 2.82mm lga ltm4628 dual, 8a, 26v, dc/dc module regulator 4.5v v in 28.5v, 0.6v v out 5.5v, remote sense amplifier, internal temperature sensing diode output, 15mm 15mm 4.32mm lga ltm4620a dual, 16v, 13a, 26a, step-down module regulator 4.5v v in 16v, 0.6v v out 5.3v, 15mm 15mm 4.41mm lga design r esources subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation tools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products search 1. sort table of products by parameters and download the result as a spread sheet. 2. search using the quick power sear ch parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management linear technologys family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. LTM4642 4642fb for more information www.linear.com/LTM4642

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